A DAC is designed to convert an m-bit digital input word into a corresponding analog output signal. The DAC includes a plurality of current sources and a plurality of switching means corresponding to the current sources. Each switching means is connected to its corresponding current source and switches the current from that current source either to a first terminal, connected to a first connection line of the converter, or to a second terminal, connected to a second connection line of the converter. Each switching means receives one of a plurality of control signals and selects either its first terminal or its second terminal in accordance with the value of the control signal concerned. An output current of the DAC is the sum of the respective currents delivered to the first connection line.
It will be appreciated that the number of current sources and corresponding switching means in a DAC is quite large, particularly when the number of bits (m) of the digital input word is large, e.g. 6 or larger. Furthermore, when using linearly weighted blocks in a DAC, the number of switches is higher than for binary weighted blocks. In order to deal with such a large number of current sources, and to enable control signals to be delivered efficiently to, the switching means, it has been proposed to arrange the current sources and switching means as a two-dimensional array of cells. Each cell includes its own current source and corresponding switching means.
Several different implementations of current matrix blocks used in DACs are known.
Conventional cell array circuitry switching is such that the activation sequence generally follows the physical order of the cells in the array, starting from row 1 and activating the cells of that row sequentially in column order, followed by row 2, and so on for each successive row of the array.
Another switching order or selection sequence is, as described in U.S. Pat. No. 6,236,346, conforming to a so-called “magic square”. In such cell array circuitry, the effects of graded and symmetrical errors within the cell array, are reduced.
U.S. Pat. No. 8,453,743 describes a symmetric decoding in the row direction of the cell array. This is done in order to reduce an integral non-linearity error due to gradient of the current sources in the row direction of the array.
In the above implementations, current sources in the array are either switched ON or OFF, i.e. they are either switched to the first connection of the array which is coupled an output thereof, or they are switched to the second connection, which is a ground connection.
If more signals would have to be generated for controlling the array of current cells, then for bigger size matrix this would represent a large area for the decoder itself, and also for routing from the decoder to the switches.